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Contributor Article: Technology / Semiconductor / Memory, Storage, Processors / Intel, Micron Technology
Through Silicon Vias Might End The Reign Of The SoC, Replacing It With The "Ball". But If So, When? Part 2.
January 2014. Minor refinements through 29 May 2014.
In part one I explained why I suspect the System Cube (SC) and "Ball" will ultimately replace most System on Chip (SoC) products, and that Micron (MU) and Intel (INTC) are leading this technology charge. In this part I offer some technical detail about why I believe the Ball's inevitable, plus some thoughts about why it might become a critical product for high performance servers even if Through Silicon Via (TSV) fabrication difficulties exist and persist for an extended period.
First please consider the elephant in the room rather strongly suggested by the Hybrid Memory Cube (HMC). To try to assess whether the SC and Ball are on the horizon, one should start by considering whether the HMC is real and significant. A review of the material presented on Micron's web site strongly suggests it's the real McCoy and that its performance is truly remarkable - it's a dramatic technical development which seems likely to impact memory markets significantly, starting in high performance sectors. As best I recall it's already in use in some Micron client demonstration and research systems, and those users confirm dramatic speed and energy conservation performance gains. (And can plainly see the hardware size reduction.) There's an open question about whether the HMC can be efficiently fabricated at this time. But its fundamental existence and remarkable performance doesn't seem to be in doubt - it's evidently quite real.
If the HMC's acknowledged to be genuine, then one must extrapolate roughly as follows: Since speed and power conservation performance are both dramatically improved by stacking TSV equipped naked memory chips and a controller chip onto one another to form the HMC, wouldn't it make sense to add an SoC chip to the stack as well, giving it immensely superior intimacy with the system's entire memory block, thus substantially improving system speed yet lowering system power? If so, a very modest first generation SC must be acknowledged as a real possibility - it's a rather simple logical extension of the HMC.
Or even better, divide the original SoC into two chips, thus substantially reducing the complexity of each, which should substantially improve chip fabrication yields, then stack both of them into the SC. That shouldn't significantly degrade intimacy related performance of the SoC itself (or perhaps not at all - or perhaps an improvement could be realized).
And if that makes sense, why not add GPU, storage, radio, and ancillary chips to the stack as well, such that the SC contains nearly every electronic block required by a product, optimizing Intimacy Technology (ITech), thus substantially improving performance yet reducing power consumption?
And why not then refine the SC by transforming it into a Ball in the course of arranging every functional block to be as physically close to every other block as Mother Nature's most perfect container geometry, the sphere, allows?
Why not indeed? These are all just logical extensions of the HMC, a device of exceptionally impressive performance which already exists. The SC and Ball are the enormous elephants in the room which stand directly behind the HMC. Elephants we've generally failed to see for some reason...
There are of course technical issues associated with adding more and more chips to an SC or Ball.
Most fundamentally, a means to efficiently fabricate tiny TSVs must become available. I explained why I think this is inevitable, or already exists, in part 1, but to repeat my view in brief terms: To the best of my knowledge there are no Natural Law barriers to this challenge, and there's massive corporate treasure related pressure to accomplish the goal. So a process will be devised in time. Or it already exists, but is being managed as a sensitive corporate secret.
There must also be a means to efficiently fabricate reliable electrical bridge connections for all the TSVs for all the chips in the stack, whether simultaneously or sequentially. I doubt this is a substantial technical barrier in part because I suspect a relatively low melting point conductive bridging paste could be used for this task (though I'm strictly speculating about this methodology), but mostly simply because the existence of the HMC indicates that a method for bridging at least a few layers of TSVs already exists. I don't know whether the current method's highly efficient and reliable, but again, I know of no Natural Law barriers standing in the way of that accomplishment, and there's immense economic pressure to develop it, so it strikes me as inevitable. Or has already been accomplished.
Thermal issues in two areas must be well managed too:
The SC or Ball must be able to dissipate heat reasonably well. But remember that even though performance will be substantially higher in an SC or Ball, total power dissipation will be substantially lower than in provincial structures because of vastly improved system intimacy. I haven't studied this issue in detail, but in my estimation if temperature rise remains an issue anyway, it'll be manageable with rather conventional heat sink design. Or it might make sense to add a few very thin low temperature coefficient heat sink layers (with vias) to the stack which extend to a heat sink structure to improve cooling further. But in my estimation heat management's unlikely to be a significant issue for any portable product targeted SCs or Balls, including moderate performance products such as leading edge laptop computers, or even in desktop computers - my guess is that rather conventional cooling methods will suffice because even though heat which must be dissipated will be concentrated into a rather small SC or Ball, total heat to be dissipated will be significantly lower due to substantially improved system intimacy. Speculating wildly, my personal instinct is that even in the case of maximum performance SCs or Balls designed for high performance servers, rather conventional heat sink technology will be sufficient to manage power dissipation requirements. However, I'm not sufficiently will informed with this issue to offer quantitative or otherwise incisive views.
Thermal expansion and contraction issues must not cause significant degradation of the structural integrity of the SC or Ball. My guess is that reliability of the electrical bridges for all the TSVs for all the chips in the stack is the primary structural integrity concern. Use of a relatively flexible conductive TSV bridging paste might resolve that issue, but I'm not a student of this matter either. But again my sense is that no Natural Law barriers stand in the way of achieving fabrication methods which yield highly reliable structural integrity, and there's immense economic pressure to develop them, so they strike me as inevitable. Or already accomplished, as might be implied in some measure by the existence of the HMC.
Otherwise I see no significant barriers and enormous competitive pressures for the SC and Ball elephants in the room to begin braying sometime relatively soon, with a powerful voice nobody will miss hearing.
However, let's consider large data server facilities in a bit more detail. Suppose TSV fabrication difficulties persist, causing unimpressive yields or consuming a lot of chip real estate, thus increasing fabrication costs. But they could nonetheless be fabricated, making rather costly production of SCs and Balls feasible. Those inefficiencies would lead to expensive end products - those who seek SCs and Balls would have to pay a premium price for them. But in the case of maximum performance SCs or Balls designed for high performance servers, a higher price would be tolerated because the superb performance and substantially lower power consumption provided by SCs or Balls would reduce the server's operational costs dramatically, yielding substantially lower costs of ownership over the life of the servers.
And as has been wisely considered in other halls by fond friends and colleagues, SoC products designed for high performance servers is a crucial business sector for Intel. Evidently Intel already dominates this arena, and its profits contribute mightily to pleasing shareholders. But if Intel and Micron introduce SC or Ball technology into this sector, they might be able to dominate it so tightly that no SoC based vendor could effectively compete for a substantial time to come - they'd be sidelined until they too were able to fabricate SCs and Balls.
So even if fabrication of TSVs is inefficient, they might still play a very important role for Intel and Micron. HMC Samples are available for customers now. Speculatively extrapolating from that, perhaps SC or Ball prototypes already reside in Intel labs behind guarded doors.
Maybe Intel's best engineers are currently optimizing performance and refining thermal management and reliability details, preparing the designs for prime time service in real world high performance servers. That's just unfounded speculation of course. However, considering the size and importance of the high performance server market, perhaps it's not an unreasonable extrapolation.
Similar speculation could be considered for Micron's Automata processor. This device seems exciting, but I don't yet have a sense for whether it will remain a substantial product differentiation compared to SCs and Balls containing rather conventional processor cores. However, perhaps it will - I don't discount that possibility. In any case the need for this type of processor seems enormous - it seems to directly address a very high growth world of applications which only data sieve specialized systems can process efficiently. It's not impossible that Automata based SCs or Balls could dominate this high growth market, enriching Micron and its stakeholders.
Watching all of this unfold will be a hoot! And my instinct is that it'll prove to be an especially gratifying drama for stakeholders, and even more so for lucky leveraged stakeholders.
But I heartily welcome vigorous constructive debate about these issues in an effort to reach a more enlightened view. It seems to me that we need the conversation - the matter strikes me as terribly important for our investing logistics. And as all my friends and colleagues will readily attest, I'm nothing even remotely like omniscient, and thus can't view these matters with as much acumen as can be achieved by the superb array of independent Micron and Intel analysts working together. So, wherever it's feasible, chime in please. Let's explore vigorously to try to find some elements of consensus wherever we can. And then leverage them by investing with rare forward insight in unusually potent human ambitions, thus directing our money into investments which will have unusually powerful constructive affect. And be rewarded handsomely for doing so...
Best of luck to all, Bruce Campbell
Relevant disclosures: Intensely long Micron common stock and call options. Significantly long Intel calls. Usually modestly long Intel common. Occasionally modestly long ChipMOS common or call options. All are long positions, and none are hedged other than quite modest precious metal common holdings. But I might divest all but my PM holdings if a serious systemic market collapse seems imminent.
This original composition expresses my personal investment views. I have no business relationship with any entity in which I hold investments.
Copyright 2014 H. Bruce Campbell, Creative Commons license: Attribution (BY) + Noncommercial (NC) + No Derivatives (ND)
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